hasersigma.blogg.se - This game requires shader model 3.0

The maximum nesting depth for loop - vs/ rep - vs is 4. (See Flow Control Nesting Limits for details.) Temporary RegistersĪ total of 32 temporary registers (r#) is supported. The maximum nesting depth value allowed is 24. Dynamic flow controlĪll dynamic flow control instructions are supported. This will produce unpredictable results on different hardware. Be careful with dynamic branching as this can cause shader outputs to vary per vertex. Similar to vs_2_0, the output of the shader can vary with static flow control. This feature allows a subset of the input registers to be initialized at a rate different from once per vertex. See Vertex Textures in vs_3_0 (DirectX HLSL).

The vertex engine has four texture sampler stages (distinct from the displacement map sampler and the texture samplers in the pixel engine) that can be used to sample textures set at those stages. This shader model supports texture lookup in the vertex shader using texldl. In this model, the following register banks can be indexed, using the loop counter register (aL): In the earlier shader models, only the constant register bank could be indexed. New features of vertex shader version vs_3_0 are listed in the following sections.

Destination Register Masking determines what components of the destination register get written.

Source Register Swizzling gives additional control over which register components are read, copied, or written.

Vertex Shader Source Register Modifiers alter the source register data before the instruction runs.

Vertex Shader Register Modifiers are used to modify the way an instruction works.

Registers - vs_3_0 lists the different types of registers used by the vertex shader ALU.

Instructions - vs_3_0 contains a list of the available instructions.

Each of the features in vs_2_X that requires a cap to be set, is available in vs_3_0 without requiring the cap. Vertex shader version vs_3_0 extends the feature set supported by vs_2_x. Additional control can be applied to modify the instruction, the results, or what data gets written out. Registers transfer data in and out of the ALU. A programmable vertex shader is made up of a set of instructions that operate on vertex data.